The present invention relates to integrated circuits capable of being used with different VCC voltage levels, and in particular to a technique of using control pins to specify the VCC or other voltage levels.
As integrated circuit and processing technology continue to evolve, the VCC and other voltage levels of the integrated circuit continue to change. Typically, VCC supply voltages are being reduced. For example, some supply voltages in use today are 5 volts, 3.3 volts, 3 volts, 2.5 volts, and 1.8 volts. Generally, integrated circuits have been designed to be used with a particular supply voltage, and not other supply voltages. This means that the integrated circuit manufacturer needs to fabricate different version of the integrated circuit for the different supply voltages. And, the customer or user needs to order and stock different versions of the same integrated circuit for the different supply voltages.
It is desirable that the same integrated circuit design can be configured to be used with multiple voltage supply voltage levels. And, it is desirable that the user can selectively configure the integrated circuit device to operate with the voltage level the user selects.
As can be appreciated, there is a need for improved techniques and circuitry for providing and integrated circuit capable of operating using multiple supply voltage levels.
The present invention provides circuitry and techniques for an integrated circuit capable of operating with multiple, different voltage levels. The integrated circuit has one or more external control pins to indicate which VCC or other voltage level will be used with the chip. The control pin receives a logic signal, high or low, and draws zero static power. A user can use the integrated circuit with two or more VCC voltage levels by indicating which voltage level at the control pins. In a specific embodiment, the integrated circuit has nonvolatile memory cells such as EEPROM or Flash cells that a configurable and reconfigurable using on-chip programming circuitry. The programming circuitry may generate and use superhigh or high voltages, higher than the VCC voltage. In a specific embodiment, the invention is an integrated circuit including an external pin; a voltage level detect circuit connected to the external pins, where the voltage level detect circuit outputs a logic signal indicative of a voltage supply level provided to the integrated circuit by a user; and an internal circuit connected to receive the logic signal, where the internal circuit modifies its operation based on the logic signal in order to operate at the user""s voltage supply level. Further, the voltage supply level may be VCC or VDD. Alternatively, the voltage supply level may be VPP. For the integrated circuit, when the voltage supply level is 5 volts, the external pin is connected to ground, and when the voltage supply level is 3 volts, the external pin is connected to the voltage supply level. The voltage level detect circuit may include a logic gate to decode data input at the external pin. The integrated circuit may be a programmable logic integrated circuit. In an embodiment, the external pin is connected only to the voltage level detect circuit of the integrated circuit. The external pin may supply zero current to the integrated circuit. The external pin receives a logic signal. In another embodiment, the external pin supplies less than one milliamp to the integrated circuit. The external pin does not supply the voltage supply level to the internal circuit.
In another embodiment, the invention is a programmable integrated circuit including a VCC level control pin and a number of input buffers, each connected to the VCC level control pin. There are a number of memory cells connected to the input buffer. A number of sense amplifiers are connected to the memory cells and the VCC level control pin, where the input buffers and sense amplifiers are configured to operate with one of at least two different VCC voltage levels based on a logic level at the VCC level control pin.
An input buffer includes a first buffer. The first buffer includes a first transistor connected to a VCC supply and a second transistor connected between the first transistor and a first buffer output node. A third transistor is connected between the first buffer output node and a ground supply, where control electrodes of the second and third transistors are connected to an input pin and sizes of the second to third transistors have a first ratio. A second buffer of the input buffer includes a fourth transistor connected to the VCC supply and a fifth transistor connected between the fourth transistor and a second buffer output node. A sixth transistor is connected between the second buffer output node and the ground supply, where control electrodes of the fifth and sixth transistors are connected to an input pin and sizes of the fifth and sixth transistors have a second ratio, different from the first ratio. A logic gate circuit of the input buffer is connected to the first and second buffer outputs and providing an input buffer output, where a control electrode of the first transistor is connected to a signal from the VCC level control pin and a control electrode of the fourth transistor is connected to an inverted version of the signal from the VCC level control pin.
A sense amplifier includes a bit line having a plurality of memory cells connected in parallel. A first pull-up transistor is connected to the bit line and has a first size. A second pull-up transistor is connected to the bit line and has a second size, different from the first size, where a control electrode of the first pull-up transistor is connected to a signal from the VCC level control pin and a control electrode of the second pull-up transistor is connected to an inverted version of the signal from the VCC level control pin.
The programming circuitry includes an oscillator circuit having a first oscillator having a first oscillator frequency and a second oscillator having a second oscillator frequency, different from the first oscillator frequency. A first logic gate is connected to the first oscillator and a signal from the VCC level control pin. A second logic gate connected to the second oscillator and an inverted version of the signal from the VCC level control pin. A third logic gate is connected to the first and second logic gates and provides an oscillator output.
A superhigh voltage detector circuit includes a first impedance divider circuit having a first ratio, connected to the superhigh voltage pin. A second impedance divider circuit has a second ratio, different from the first ratio, and is connected to the superhigh voltage pin. A multiplexer circuit is connected to the first and second impedance divider circuits, where a selection input of the multiplexer is connected to the VCC level control pin and the multiplexer outputs a superhigh voltage control signal.
In another embodiment, the invention is a programmable logic integrated circuit including a VCC level control pin, a plurality of input buffers, each having an adjustable input threshold voltage which is varied based on the VCC level control pin. A plurality of memory cells are connected to the input buffers. A plurality of sense amplifiers are connected to the memory, cells where each sense amplifier has an adjustable trip point which is varied based on the VCC level control pin. A plurality of configurable logic circuits, connected to the sense amplifiers, are programmable by a user to implement logical functions. Programming circuitry is connected to the sense memory cells including an oscillator circuit having an adjustable oscillator frequency which is varied based on the VCC level control pin.